# Why do we need transmission gate for XOR (transistor level design)?

The following image shows a 6-transistor XOR circuit.

But I don't know why the last 2 gates are needed at all, the circuit can be simplified to:

Is there anything that prevents us from using the last circuit? I tested all 4 scenarios of (A,B) = (0,0) (0,1) (1,0) (1,1), all of them gives a correct answer.

• Nobody says you need it, and this is one only one way in which a XOR can be made. It's one of the drawbacks of the pass transistor logic: the levels are almost never fully 0 or fully 1 without some sort of signal level restoring. There's also fan out/in to be considered. May 22 at 16:44

There are practical concerns with real transistors that you do not see in the digital diagram. MOSFETs require the correct difference between the gate and source terminals to conduct. You can always find the answer to "why is the digital diagram more complicated than it needs to be?" by thinking of the transistors as real transistors...which they are.

The problem here is that because the second push-pull stage is pretty weird how the source terminals do not connect to power rails so you can't just apply a LO to the PMOS gate in the second stage and expect it to conduct. I didn't realize there were logic circuits that would do something like this.

In all, whenever (0,X), the second push-pull stage is incapable of driving the output so the transmission gate is required. In particular, look at the case (0,0) where the second stage's PMOS source and gate terminal have the same voltage applied so the Vgs = 0 so it can't conduct even if are applying a 0 to the gate. The NMOS experiences the same problem for (0,1).

Conversely, whenever (1,X) the transmission gate is incapable of driving the output so the second push-pull stage is required.

Pretty interesting...the second stage is an inverter for B while the transmission gate is a pass-through for B and which one gets used on B is controlled by the state of A.

The 4-transistors circuit behaves like a bad XOR gate. When A=0, the second NMOS/PMOS acts like a bad buffer, for B = VDD => Y = VDD - Vthn, for B=0 => Y=Vthp (the capacitances at node Y will never fully charged/discharge to VDD or 0).

I think the transmission gate is to make another path to charge/discharge capacitances at node Y when A=0 (disable when A=1).For example, AB = 01 and Y is initially 0, capacitances at Y is charged through the NMOS and the transmission gate. Whenever Y reaches VDD - Vthn, the NMOS turns off but the transmission gate keep charges up node Y to VDD.

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