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1   Introduction

triSYCL is a research project to experiment with the specification of the SYCL standard and to give feedback to the Khronos Group SYCL_committee and also to the ISO C++ committee.

Because of lack of resources this SYCL implementation is very incomplete and should not be used by a normal end-user. Fortunately there are now several strong implementations of SYCL available, such as ComputeCpp, DPC++ or hipSYCL that can be used on various targets.

This implementation is mainly based on C++17 with increasing C++20 features backed with OpenMP or TBB for parallel execution on the CPU, with Boost.Compute for the non single-source OpenCL interoperability layer and with an experimental (but now obsolete 2017-2018) LLVM/Clang version for the device compiler providing full single-source SYCL experience, typically targeting a SPIR device. Since in SYCL there is a host fall-back, this CPU implementation can be seen as an implementation of this fall-back too.

Since around 2018 Intel put a lot of effort in their own DPC++ project to up-stream SYCL into LLVM/Clang, there is another project about merging the Intel SYCL implementation with triSYCL at to give a greater user experience for Xilinx FPGA instead of using our experimental clunky device compiler. But this is still very experimental because the Xilinx tool-chain is based on old incompatible versions of LLVM/Clang.

Most of our efforts are focused on extensions, such as supporting Xilinx FPGA and Versal ACAP CGRA, which is not open-source yet since it would expose too much architectural details for now.

triSYCL has been used to experiment and provide feedback for SYCL 1.2, 1.2.1, 2.2, 2020 and even the OpenCL C++ 1.0 kernel language from OpenCL 2.2.

This is provided as is, without any warranty, with the same license as LLVM/Clang.

Technical lead: Ronan at keryell point FR. Developments started first at AMD and are now mainly funded by Xilinx.

It is possible to have a paid internship around triSYCL, if you have some skills related to this project. Contact the technical lead about this. Xilinx is also hiring in this area... :-)

2   SYCL

SYCL is a single-source modern C++-based DSEL (Domain Specific Embedded Language) aimed at facilitating the programming of heterogeneous accelerators by leveraging the OpenCL language and concepts.

A typical kernel with its launch looks like this pure modern C++ code:

queue {}.submit([&](handler &h) {
    auto accA = bufA.get_access<access::mode::read>(h);
    auto accB = bufB.get_access<access::mode::write>(h);
    h.parallel_for<class myKernel>(myRange, [=](item i) {
        accA[i] = accB[i] + 1;

Look for example at for a complete example.

Note that even if the concepts behind SYCL are inspired by OpenCL concepts, the SYCL programming model is a very general asynchronous task graph model for heterogeneous computing with no relation with OpenCL itself, except when using the OpenCL API interoperability mode.

SYCL is developed inside the Khronos SYCL committee and thus, for more information on SYCL, look at

For the SYCL ecosystem, look at

3   Documentation

3.1   Some reasons to use SYCL

Please see about SYCL to have some context, a list of presentations, some related projects.

3.2   Installation & testing

SYCL is a template library, so no real installation is required.

There are some examples you can build however.

See Testing.

3.3   Architecture of triSYCL runtime and compiler

Architecture of triSYCL runtime and compiler describes the code base with some high-level diagrams but also how to compile and use the device compiler on some Xilinx FPGA for example.

3.4   CMake infrastructure

Some details about CMake configuration and organization can be found in CMake.

3.5   Pre-processor macros used in triSYCL

Yes, there are some macros used in triSYCL! Look at Pre-processor macros used in triSYCL to discover some of them.

3.6   Environment variables used in triSYCL

See Environment variables with triSYCL.

3.7   Possible futures

See Possible futures.

3.8   triSYCL code documentation

The documentation of the triSYCL implementation itself can be found in and

4   News

  • 2018/03/12: the long-going device compiler branch has been merged in to provide experimental support for SPIR-df friendly devices, such as PoCL or Xilinx FPGA. This is only for the brave for now.
  • 2018/02/01: there is now some documentation about the architecture of triSYCL on GPU and accelerators with its device compiler based on Clang/LLVM in doc/architecture.rst. While this is wildly experimental, there is a growing interest around it and it is always useful to get started as a contributor.
  • 2018/01/05: there are some internship openings at Xilinx to work on triSYCL for FPGA and more generally Xilinx is hiring in compilation, runtime, C++, SYCL, OpenCL, machine-learning...
  • 2017/12/06: the brand-new SYCL 1.2.1 specification is out and triSYCL starts moving to it
  • 2017/11/17: the presentations and videos from SC17 on SYCL and triSYCL are now online
  • 2017/09/19: there is a prototype of device compiler based on Clang/LLVM generating SPIR 2.0 "de facto" (SPIR-df) and working at least with PoCL and Xilinx SDx xocc for FPGA.
  • 2017/03/03: triSYCL can use CMake & ctest and works on Windows 10 with Visual Studio 2017. It works also with Ubuntu WSL on Windows. :-) More info
  • 2017/01/12: Add test case using the Xilinx compiler for FPGA
  • 2016/11/18: If you missed the free SYCL T-shirt on the Khronos booth during SC16, you can always buy some on (lady's sizes available, so no excuse! :-) )
  • 2016/08/12: OpenCL kernels can be run with OpenCL kernel interoperability mode now.
  • 2016/04/18: SYCL 2.2 provisional specification is out. This version implement SYCL 2.2 pipes and reservations plus the blocking pipe extension from Xilinx.


Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group







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