Not every manufacturing node comes out perfectly and not every one comes out on time, but in the past decade and a half, Taiwan Semiconductor Manufacturing Co, the world’s largest and most technologically advanced etcher of chips in the world, has done far better than any of its few remaining peers to push the chip manufacturing envelope while also maintaining consistent and profitable production of older nodes.
TSMC is itself a money making machine. If you double its capital expenses over three years it doubles its revenues and profits over five years, something that Sebastian Hou, senior investment analyst at Neuberger Berman, observed in a call TSMC did with Wall Street going over the fourth quarter 2021 financial results for the foundry.
CC Wei, TSMC’s chief executive officer, and Wendell Huang, the company’s chief financial officer, did not endorse applying this algorithm out to the future performance for the company – “things are not that simple,” as Huang put it, adding that the complexity of chip making equipment and the chips themselves as well as the lead time to get equipment is getting longer, which might put more of a time lag between when capital is spent and revenue is generated.
What can be said is that TSMC invests ahead of demand, and companies wanting to ensure that their chips will get made are increasingly prepaying for their wafer and packaging agreements, which is helping TSMC keep more of its own cash on hand even as it is making enormous investments in foundry capacity. Actually, the math is compelling. In 2019, TSMC spent $14.9 billion on capital expenses while it generated $34.6 billion in revenues mostly from investments in prior nodes; in 2020, the foundry spent $30 billion in 2021 and generated $56.8 billion revenues. Capital expenses are a leading indicator for future revenues and potential future profits of the top brass at TSMC keep an iron hand on costs and can keep extracting more revenue from each wafer they etch. Take the capex from two years ago, multiple by a little less than 2X, and you can predict revenues for this year. Each year, because of the increasing complexity of chip fabrication and packaging processes, you shave a little more from this ratio.
The real question is when does chip making get so hard that the capex to revenue ratio falls lower and lower, and can it actually get close to 1.0? And what might that mean for both revenues and profits? In the short term, TSMC has a lot of money in the bank and can afford to keep investing in fabs as well as fundamental research to help customers make chips using its N7, N5, and N3 processes and their variants. So we can breathe easy for now. So long as China doesn’t start feeling proprietary about the island of Taiwan. . . .
Let’s back up and start at the top and bottom line, and then get into what TSMC is making and what is driving revenues and what process nodes are driving current sales and what ones will be driving future ones.
In the fourth quarter of 2021, TSMC’s revenues rose by 6.2 percent, the first time growth was in the single digits in a year and a half, and net income rose by only 7.2 percent to $5.96 billion. Every two years or so, there is a tremendous amount of investment in future nodes at the same time as new processes are being brought online, but we suspect there is another culprit at work for the slowing of revenue and profit growth: TSMC is at capacity and can’t add capacity fast enough to meet demand.
While revenues and profits set new records for TSMC in Q4 2021, what we can’t see in any of these numbers is the revenue that has been left on the table because TSMC has demand from its chip designer customers that it cannot meet; we can’t easily see the downstream affects of that impedance mismatch between manufacturing capacity for any given node and manufacturing capacity at TSMC, but we think that if more wafers were available, companies like Nvidia and AMD would be generating more revenue than they have been doing. Mitigating against this is the fact that TSMC can charge more money for its most advanced processes and chip designer/sellers, in turn, can charge a premium for their devices, and the revenues and profits keep moving up and to the right.
Two years ago, TSMC set forth a three-year plan to spend $100 million on expanding its chip and packaging capacity and do the primary research and development to bring 7 nanometer N7 and 5 nanometer N5 processes to market, but at this point, with so much uncertainty in the world, TSMC is only talking about spending somewhere between $40 billion and $44 billion on capex in 2022. And unlike Intel, TSMC actually has more than enough cash and investments to do its foundry investments.
To be fair, as the chart above shows, TSMC was spending it as fast as it could make it in the wake of the Great Recession, which was also when the wave of GPU accelerators for datacenter compute, GPUs for gaming, and high spend networking all combined to make a powerhouse manufacturer of CPU, GPU, FPGA, and network ASIC chips. This is what TSMC has referred to as its “HPC” business in its financial presentations for the past three years and which was backcast into 2018.
TSMC’s business is dominated by the chips it makes for smartphones, which accounted for $6.92 billion in of sales in the fourth quarter of 2021, which was 44 percent of total sales, but the HPC segment is a close second with $5.82 billion in revenues in the period, which is 37 percent of revenues. Revenues from etching smartphone chips were down 8.4 percent in Q4 2021, which was better than the typical seasonal decline, while sales in the HPC segment were up 26.7 percent, largely through high demand for top-end CPUs and GPUs. The hodgepodge of chips aimed at IoT, digital consumer electronics, automotive, and other sectors comprised $2.99 billion in sales in the quarter, up 12.1 percent year on year.
Most foundries have a mix of machines that etch chips on 200 mm (8-inch) and 300 mm (12-inch) wafers, and in recent years TSMC has talked about 12-inch wafer equivalents to normalize for wafer size across its equipment to give Wall Street a sense of its quarterly wafer shipments. Until 2012, TSMC talked about 8-inch wafer equivalents, and we have converted this data from 2005 through 2012 into 12-inch wafer equivalents to normalize it. As you might expect, there is a very tight relationship between the number of wafers pumped through the foundries and the revenues.
In the past three years, even before the coronavirus pandemic started, TSMC revenues grew slightly faster than wafer shipments, which shows the premium that TSMC can charge, especially for its most advanced processes, which are literally second to none on planet Earth right now.
In Q4, TSMC shipped a record 3.73 million wafers, generating an average of $4,225 per 12-inch wafer equivalent. That’s the second-best average revenue per wafer TSMC has ever turned in, and the top was a year ago when it had $14.82 million in revenues and shipped 3.25 million wafers for an average of $4,566 per wafer.
Another factor in play is that chip designer/sellers are stocking up on inventory – and paying for it – to help alleviate supply chain issues that are hobbling parts of the datacenter sector as well as other places where semiconductors are embedded into products. (Which means everything, really.)
“Entering 2022, we expect the supply chain to maintain a higher level of inventory as compared to the historical seasonal level given the industry’s continued need to ensure supply security,” Wei explained on the call with Wall Street. “While the short-term imbalance may or may not persist, we continue to observe the structural increase in long-term semiconductor demand underpinned by the industry megatrend of 5G and HPC-related applications. We also observed the higher silicon content in many end devices, including automotive, PCs, servers, networking and smartphones. As a result, we expect our capacity to remain tight throughout 2022 as we believe our technology leadership will enable TSMC to capture the strong demand for our advanced and specialty technologies.”
Wei added that the HPC segment – and remember, this does not mean HPC simulation and modeling, but datacenter CPUs, GPUs, NPUs, FPGAs, switch and adapter ASICs, and custom ASICs for compute – “will be the strongest driver of TSMC’s long-term growth” and the company expects it to be the biggest contributor of its incremental growth as it looks ahead over the next few years. Together, 7 nanometer and 5 nanometer processes accounted for 50 percent of wafer revenue in Q4 2021, up 9 points from the year ago period.
Looking ahead to Q1 2022, TSMC expects for sales to be between $16.6 billion and $17.2 billion, which will be another record and which is 7.4 percent growth at the midpoint of that range compared to Q1 2021. Wei spoke only generally about the company’s forecast for all of 2022, saying that, ignoring memory, which TSMC does not make, the chip market is expected to grow by 9 percent, the overall foundry market is expected to grow by close to 20 percent, and that TSMC will be its industry peers by growing in the middle to high 20 percents when reckoned in US dollars.
Wei talked a bit about the status of current and future process nodes, allaying some of the fears around the 3 nanometer N3 processes (there will be a few of them) that gave chip designer/sellers heart palpitations early last summer. (See The Chip Has Hit The Fan for more on that.) Let’s start with the 5 nanometer (that’s a very general term) N5 family of processes.
N5 started ramping three years ago and is one of the most successful nodes in the company’s long history, being widely adopted for smartphone chips, desktop and server CPUs, desktop and server GPUs, and other devices in the datacenter. TSMC has tweaked the N5 process to create the N4P and N4X variants. The N4P process, according to Wei, offers an 11 percent transistor performance bump over the initial N5, with a 22 percent improvement in power efficiency and a 6 percent increase in transistor density; the first tape-outs of chips using N4P will begin in the second half of 2022. After that comes N4X, which is a further optimization aimed at “workload-intensive HPC applications,” which means high performance CPUs, GPUs, and switch ASICs, we presume. As is the case with server transistors in any given process, the N4X process will have a significant transistor performance boost over N5 and N4P and will enter “risk production” – what software people call alpha and beta testing – in the first half of 2023.
The N3 process, mentioned above, will use FinFET 3D transistor techniques like the N7 and N5 processes did and will shrink transistors features to the equivalent of 3 nanometers. (Don’t get us started about how these terms are increasingly meaningless. We know. The way we explain it is that these transistor etching techniques give features equivalent of what you would get with transistors etched in a 2D planar format with 3 nanometer gate pitch. And even that is not precise enough.) N3 production will start in the second half of 2022 for HPC and smartphone applications and “development is on track,” according to Wei, who added that the company expects more tapeouts with the initial N3 than happened with the initial N5. (Which implies Intel will be using it, unlike the early N5.) N3E, which is an enhanced N3 node with more performance, better power efficiency, and higher yield is on track for the second half of 2023. TSMC expects for the N5 and N3 nodes to be “large and long lasting.” Which is funny, we can’t imagine past the N2 node to the N1 and N0 nodes at all.
One last interesting tidbit. Of the $40 billion to $44 billion in capex that TSMC will spend in 2022, somewhere between 70 percent and 80 percent of that will be spent on gear for the N7, N5, N3, and N2 nodes, another 10 percent will be spent on advanced packaging technology research and development, and 10 percent to 20 percent will be spent on “specialty technologies,” whatever they might be.